This application is based on application No. 2002-93878 filed in Japan, the contents of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to high-speed operation of an A/D converter circuit.
2. Description of Related Art
FIG. 10 shows a conventional A/D converter, more precisely, it is a four-bit output type series-parallel A/D converter. The A/D converter includes: high-order comparators COMP11, 12, and 13 controlled by control signals 1A, 1B, and 1C, outputted from a high-order-comparator control circuit 10; and low-order comparators COMP21, 22, and 23 controlled by control signals 2A, 2B, and 2C outputted from a low-order-comparator control circuit 20. Input terminals (IN) of respective comparators COMP11, 12 and 13, COMP21, 22, and 23 are connected to an input terminal (AIN) of the A/D converter. To reference voltage terminals of the respective comparators, there are appropriately selected and inputted various levels of voltage obtained by dividing input voltage range of analog-input voltage VAIN (maximum reference voltage: VRH, minimum reference voltage: VRL) into sixteen by a ladder-resistance-element array.
The reference voltage terminals (REF) of the high-order comparators 11, 12, and 13 are connected to voltage-divided terminals (N1), (N2), and (N3), respectively, obtained by dividing the input voltage range of the analog-input voltage VAIN into four by the ladder-resistance-element array. At the time of A/D conversion, firstly, voltage level of the analog-input voltage VAIN is roughly detected and A/D conversion of high-order bits is conducted. Output terminals (011), (012), and (013) are connected to a switch selecting circuit 30. From the switch selecting circuit 30, there is selectively inputted any one of switch control signals S1 through S4 depending on an A/D conversion result of high-order bits.
The reference voltage terminals (REF) of the low-order comparators COMP21, 22, and 23 are connected to voltage-divided terminals of the ladder-resistance-element array through a change-over switch groups SW1 through SW4. The change-over switch groups SW1 through SW4 are alternatively selected in accordance with types of switch control signals S1 through S4. Thereby, low-order reference voltage of the low-order comparators COMP21, 22, and 23 is determined. That is, in case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN1 at a voltage-divided terminal of the ladder-resistance-element array, the change-over switch group SW1 is selected and low-order reference voltages VN01, VN02, and VN03 are inputted to the reference voltage terminals of the comparators COM21, 22, and 23, respectively. It should be noted that, in the precedent passage and following passages, voltage level of each voltage-divided terminal is indicated with a prefix xe2x80x9cVxe2x80x9d to a name of a voltage-divided terminal. Similar to the above case, in case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN2 and lower than VN1, the change-over switch group SW2 is selected and low-order reference voltages VN11, VN12, and VN13 are inputted. In case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN3 and lower than VN2, the change-over switch group SW3 is selected and low-order reference voltages VN21, VN22, and VN23 are inputted. In case the analog-input voltage VAIN is lower than VN3, the change-over switch group SW4 is selected and low-order reference voltages VN31, VN32, and VN33 are inputted.
A four-bit output can be obtained with the following manner. That is, bits of an output is divided into high-order bits and low-order bits and then, logic level of outputs 011, 012, 013, 021, 022, and 023 from the comparators COMP11, 12, and 13, and the comparators COMP21, 22, and 23, respectively, are encoded.
FIG. 11 shows operational waveforms. The A/D converter of FIG. 10 operates in synchronous with a clock signal CLK. The A/D converter takes a (xc2xd)-period of a clock signal CLK as a time step for its operation. Three operation states, namely, fetch operation of the analog input voltage VAIN (I), holding operation of the fetched voltage (II), and voltage comparison operation (III) are switched every time step. Time steps {circle around (1)} through {circle around (5)} make an operation unit and A/D conversion operation is conducted.
During a time step {circle around (1)}-{circle around (2)}, a high-order comparator COMP1x (x=1, 2, and 3, same as the following descriptions) and a low-order comparator COMP2x fetch the analog-input voltage VAIN (operation (I)). Voltage level fetched at this time step shifts to maximum voltage level VRH from voltage level VN1X that is same as or higher than high-order reference voltage VN2 at a terminal (N2) of the ladder-resistance-element array and lower than high-order reference voltage VN1 at the terminal N1. Capacitance components with respect to internal terminals of the comparators COMP1x and COMP2x are charged up to voltage level VRH for the analog-input voltage VAIN.
Next, during a time step {circle around (2)}-{circle around (3)}, each of the low-order comparators COMP2x holds voltage level VRH (operation (II)), and each of the high-order comparators COMP1x shifts to comparison state (operation (III)). Voltage level at internal terminals of respective high-order comparators COMP1x makes transitions from the maximum voltage level VRH to respective high-order reference voltage VNx (x=1, 2, and 3, same as the following descriptions) through the reference voltage terminals (REF). As a result, from the reference voltage terminals (REF) of respective high-order comparators COMP1x, there flows current due to charge and discharge from the capacitance components of the internal terminals. FIG. 11 shows a case of the high-order comparator COMP11. Outflow current of peak current 1100 flows out due to discharge. The outflow current flows toward a terminal (RL) in the ladder-resistance-element array. Therefore, voltage rise in proportion to outflow current reflects level of the low-order reference voltage VN01 at the voltage divided terminal (N01) as amount of voltage fluctuation. It is assumed that peak voltage corresponding to the amount of voltage fluctuation is V100.
Next, during a time step {circle around (3)}-{circle around (4)}, low-order reference voltage is set prior to comparison operation of respective low-order comparators COMP2x. Based on comparison results of respective high-order comparators COMP1x, a change-over switch group to be determined by the switch selecting circuit 30 is selected. In case of FIG. 11, change-over switch groups are changed from the change-over switch group SW2 for voltage level VN1X at a precedent cycle to the changeover switch group SW1 suitable to voltage level VRH. Due to changeover of the switch groups, capacitance components Cp1, Cp2, and Cp3 between each of the change-over switch groups SW1 through SW4 and each of the low-order comparator COMP2x are charged, whereby terminal voltage makes transition from voltage level VN1 to VRH. At this stage, current is supplied from a terminal (RH). Consequently, low-order reference voltage VN01 at the voltage-divided terminal (N01) is heightened. It is assumed that an amount of voltage fluctuation at this stage is V2. It should be noted that the capacitance components Cp1, Cp2, and Cp3 are equivalent to a sum of parasitic capacitance components obtained at each of the change-over switch groups SW1 through SW4, each of the low-order comparators COMP2x, and wirings.
Further on, during a time step {circle around (4)}-{circle around (5)}, each of the high-order comparators COMP1x keeps comparison state (operation (III)) and the each of the low-order comparators COMP2x shifts to comparison state (operation (III)). Internal terminals of respective low-order comparators COMP2x at this stage work in a same manner as those of respective high-order comparators COMP1x at the time step {circle around (2)}-{circle around (3)}. That is, voltage level at internal terminals of respective low-order comparators COMP2x makes transition from the maximum voltage level VRH to respective low-order reference voltage VN0x (x=1, 2, and 3, same as the following descriptions) through the reference voltage terminals (REF). Since a width of transiting voltage at the time step {circle around (4)}-{circle around (5)} is narrower than at the time step {circle around (2)}-{circle around (3)}, an amount of voltage fluctuation from a set value of peak voltage is V3 ( less than V100).
Not to mention, though FIG. 11 shows voltage-level transition of the low-order reference voltage VN01 only as an example, voltage level of the other low-order reference voltage VNO2 and VNO3 makes transition in a same manner as VNO1.
However, in the conventional A/D converter, each of the high-order comparators COMP1x keeps comparison state and each of the high-order reference voltages VNx is supplied to each of corresponding reference voltage terminals (REF) during a time step of {circle around (2)}-{circle around (5)}. Electric current is charged/discharged until voltage level at the internal terminals of the high-order comparators COMP1x makes transition from voltage level of the analog-input voltage VAIN fetched at the time step {circle around (1)}-{circle around (2)} to respective high-order reference voltages VNx. Voltage transition at the internal terminals at this stage may be almost full-wide voltage transition between the maximum voltage level VRH and the minimum voltage level VRL within a input voltage range though it depends on voltage level of the analog-input voltage VAIN.
Therefore, as shown in FIG. 11, there may be a case that voltage transition of the internal terminals does not finish within a time step {circle around (2)}-{circle around (3)}. In that case, due to outflow current from the reference voltage terminals (REF) caused by the voltage transition of the internal terminals (i.e., in case voltage level of fetched analog-input voltage VAIN is higher than the high-order reference voltage VNx), voltage levels of respective high-order and low-order reference voltages, set by the ladder-resistance-element array, deviate from their respective set values in time steps after time {circle around (3)}. Deviation of the reference voltage caused by comparison operation of the respective high-order comparators COMP1x may remain at subsequent state, i.e., comparison state of the respective low-order comparators COMP2x (time step {circle around (4)}-{circle around (5)}) without being cleared. As a result, at the respective low-order comparators COMP2x, comparison operation is conducted with low-order reference voltage deviating from set value. With comparison operation as such, accurate voltage comparison results cannot be obtained, which is problematic.
As oscillation frequencies of clock signal CLK to operate the conventional A/D converter are generated faster, deviation voltage values turns out more apparent. Therefore, under the trend that higher-speed operation is sought for A/D converters, conversion errors such as the conventional A/D converter become a much more serious problem.
The present invention is made to solve the above-mentioned problem. Accordingly, it is an object of the present invention to provide an A/D converter circuit capable of high-speed operation without fluctuation of high-order reference voltage caused by comparison operation of high-order comparators influencing on voltage level of low-order reference voltage at the time of comparison operation of low-order comparators.
To achieve the object, according to one aspect of the present invention, there is provided an A/D converter circuit comprising: one or more voltage comparators for conducting A/D conversion; and a resistance-component-element array for generating respective reference voltage(s) for the respective voltage comparator(s) at each voltage-divided terminal of the resistance-component-element array; wherein the A/D converter circuit further includes reference voltage holding section(s) for holding the respective reference voltage(s) supplied from each voltage-divided terminal and supplies the respective reference voltage(s) held thereat to the respective voltage comparator(s) after each of the voltage-divided terminal(s) is electrically separated from the respective reference voltage holding section(s)
In the A/D converter circuit according to the one aspect of the present invention, the respective reference voltage(s) is/are generated at each voltage-divided terminal of the resistance-component-element array as reference voltage(s) for the respective voltage comparator(s). The respective reference voltage(s) is/are firstly supplied to the respective reference voltage holding section and held there. After that, the respective reference voltage holding section(s) is/are separated from each of the voltage-divided terminal(s) and the respective reference voltage(s) held is/are supplied from the respective reference voltage holding section(s) to the respective voltage comparator(s).
While reference voltage(s) generated at the each voltage-divided terminal of the resistance-component-element array is/are supplied to and held at the respective reference voltage holding section(s), reference voltage(s) to be supplied to the voltage comparator(s) can be supplied to the voltage comparator(s) from the reference voltage holding section(s) after the each voltage divided terminal is separated from the reference voltage holding section(s). Accordingly, voltage fluctuation never occurs to voltage-divided terminals of the resistance-component-element array when reference voltage(s) is/are supplied to the voltage comparator(s).
Furthermore, according to another aspect of the present invention, there is provided an A/D converter circuit comprising: one or more high-order-bit-discrimination voltage comparators for conducting A/D conversion of high-order bits prior to A/D conversion of low-order bits; and a resistance-component-element array for generating each high-order reference voltage for A/D conversion of each of the high-order bits at each high-order-voltage-divided terminal, and each low-order reference voltage for A/D conversion of each of the low-order bits at each low-order-voltage-divided terminal, the resistance-component-element array being connected between high-voltage-side reference voltage and low-voltage-side reference voltage; wherein the A/D converter circuit further includes each reference voltage holding section for holding each high-order reference voltage supplied from each high-order voltage-divided terminal and supplies each high-order reference voltage held thereat to each high-order-bit-discrimination voltage comparator after each high-order-voltage-divided terminal is electrically separated from the each reference voltage holding section.
In the A/D converter circuit according to another aspect of the present invention, each high-order reference voltage is generated at each high-order-voltage-divided terminal of the resistance-component-element array as reference voltage for each high-order-bit-discrimination voltage comparator. Each high-order reference voltage is firstly supplied to each reference voltage holding section and held there. After that, each reference voltage holding section is separated from each high-order-voltage-divided terminal and each high-order-reference voltage held is supplied from each reference voltage holding section to each high-order-bit-discrimination voltage comparator(s).
While high-order reference voltage generated at the high-order-voltage-divided terminal of the resistance-component-element array is supplied to and held at the reference voltage holding section, high-order-reference voltage to be supplied to the high-order-bit-discrimination voltage comparator(s) can be supplied to the high-order-bit-discrimination voltage comparator(s) from the reference voltage holding section after the high-order-voltage-divided terminal is separated from the reference holding section. Accordingly, voltage fluctuation never occurs to a high-order-voltage-divided terminal of the resistance-component-element array when high-order reference voltage is supplied to the high-order-bit-discrimination voltage comparator(s). Furthermore, at the time of A/D conversion of low-order bits, conducted in subsequent to high-order bits, voltage fluctuation never remains in low-order reference voltage. That is, there can be eliminated influences due to A/D conversion of high-order bits at the time of A/D conversion of low-order bits.
Furthermore, there is no need to take time for relaxation of voltage fluctuation with respect to high-order reference voltage at the high-order-divided-voltage terminal of the resistance-component-element array. Accordingly, there is no need to set unnecessary relaxation time between A/D conversion of high-order bits and A/D conversion of low-order bits. High-speed operation thus can be achieved.